verilog |
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| • | Verilog is a hardware description language (HDL) used to model electronic systems. The language (sometimes called Verilog HDL) supports the design, testing, and implementation of analog, digital, and mixed-signal circuits at various levels of abstraction. The designers of Verilog wanted a language with syntax similar to the C programming language so that it would be familiar to engineers and readily accepted. The language has a pre-processor like C, and the major control keywords such as "if", "while", etc are similar. The formating mechanism in the printing routines and language operators (and their precedence) are also similar. The language differs in some fundamental ways. Verilog uses Begin/End instead of curly braces to define a block of code. The definition of constants in verilog require a bit width along with their base, consequently these differ. Verilog doesn't have structures, pointers, or recursive subroutines either. Finally, the concept of time —so important to an HDL— won't be found in C. The language differs from a conventional programming language in that the execution of statements is not strictly linear. A Verilog design consists of a hierarchy of modules. Modules are defined with a set of input, output, and bidirectional ports. Internally, a module contains a list of wires and registers. Concurrent and sequential statements define the behaviour of the module by defining the relationships between the ports, wires, and registers. Sequential statements are placed inside a begin/end block and executed in sequential order within the block. But all concurrent statements and all begin/end blocks in the design are executed in parallel. A module can also contain one or more instances of another module to define sub-behavior. A subset of statements in the language is synthesizable. If the modules in a design contain only synthesizable statements, software can be used to transform or synthesize the design into a net Source: [wikipedia: verilog] |
hardware_description_languages:design
| ASIC World | ||
| verilog tutorial, digital electronics tutorial. with sample questions asked in interviews. links to free tools and books. examples. | ||
| International Cadence Usergroup | ||
| information on conference 2003, conference archives, a special interest group and faq. | ||
| Project VeriPage | ||
| your one stop source for verilog programming language interface (pli) resources | ||
| Source Navigator for Verilog | ||
| a version of source navigator that works with verilog. provides class and hierarchy views of verilog designs. | ||
| Verilog HDL Toolbox | ||
| by simucad. 64-bit verilog hdl simulation products for fpga and asic design and test. included are a verilog hdl finite state machine editor, waveform viewer, and chromocoded text editor. | ||
| Verilog Quicktart | ||
| book by james m. lee. details on the book and a interactive verilog faq. | ||
| Verilog.net | ||
| directory of verilog documents, tutorials, tools, vendors, books. | ||
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